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Low-Power Logical & Physical Synthesis
Overview: Development of new technology for IC compiler & Design compiler which allows a semiconductor vendors to design chips which can have different modules operating at different voltages, thus better optimizing power & speed. This involves being able to synthesis a designers specifications taking into consideration how the different power's flow and switching-on & off various sections of the chip. This is one of the latest and hottest semi-conductor technologies which needs a lot of work before it can be completely automated providing a much lesser turn-around time for such chips in future.
Key Role : I am one of the 2 initial developer for Synopsys Multi-voltage/low-power flow. This included supporting the infrastructure and its enhancements, handling the special cells like level-shifters/isolation cells, switch cells, always-on cells etc and the entire flow right from voltage areas in the floorplan, the library modelling of special cells, synthesis and placement for special cells as well as general voltage areas.
I am also an active member of Synopsys committee for “Accelera -Unified Power Format” effort and its version 1.0 implementation in the physical design. The task involves working with other synopsys groups to understand their UPF requirements and aligning it with Physical Synthesis requirements. Currently studying the UPF 2.0 proposal and estimating the future effort and project plans,
Projects
- Voltage area creation and placement : The first project in low-power designs, implemented the definition of a voltage area in the tool and modified the placement interfaces to place cells within defined boundaries.
- Infrastructure for low-power constraints: Worked in data model and constraints to store the necessary information for low power designs.
- Library syntax and modeling for special cells : The low power designs require special cells like level-shifters, isolation cells, mtcmos switches etc. I wrote the specifications for their syntax after consulting with library vendors and were incorporated in synopsys’ liberty syntax.
- Synthesis and placement of special cells : The above mentioned cells need to be inserted in the logical netlist (circuit) and later placed based on physical constraints. I did the projects to implement the handling of special cells features, both logical & physical.
- Low Power optimizations: I had implemented two optimizations for low power flows. First , the ability to restrict the type of cells that can be used for each voltage areas based on libraries and second, to have synthesis for paths that require power all the time using standard cells.
- Prototyped verilog writer for power connectivity : I did the initial prototype to enable the existing writer to also write out connectivity for power. This was later developed as solution for power specification in Synopsys flow.
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Projects ideas and specifications for team
- Low Power reports : The initial flow lacked the ability to track and report the constraints for low power. Thus I created the initial project specification document with details of the requirements. I later supervised the implementation of the project by our offshore team.
- Low power design checks : I initiated and wrote the requirement and specification for checking the correctness and feasibility of various low power constraints. This project was again implemented by our offshore team.
Low Power Flow Consultations
- Contributed as a team member for Unified Power Format effort.
- Provided valuable contributions to development of power constraints for synthesis flow (power domains)
- Worked with other product groups like relative placement technology, multi-mode/multi-corner and floorplanning teams in their efforts to migrate to a low power flow.
Miscellaneous contributions
- Critical customer engagements : Have worked on numerous engagements that were essential for adoption of technologies by the users and to build customer confidence in synopsys solutions.
Understand the competitive nature of Synopsys business and define long term projects. I came up with list of enhancements/ improvements that can help the multi-voltage solution in future. This includes both runtime and analysis related enhancements and projects. Some of the analysis would not only help in reducing the MV support but should also pave way to identify and solve issues like physical feedthru, route-estimation guidance , disjoint voltage areas, automatic AO bounds generations etc
- Improve the team effectiveness and inter-team knowledge building
- Took steps to bring the GUI features to the notice of various groups/teams so that they can use them better in debugging customer designs.
- Creating guidelines for working with new and offshore teams, such that it leads to a win-win situation for all rather than conflict of interests
Language : Synopsys software is essentially in ‘C’, it has huge code base > 1M , perhaps my contribution during the job period might be close to 100k. |
