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ASHIM GUPTA

e-mail: ashimg@synopsys.com

Present Address:
1282 Vicente Dr #C
Sunnyvale,CA-94086

Permanent Address:
A-2/248,Janakpuri,
New Delhi - 110058
INDIA

Sr R&D Engineer-I
Synopsys Inc,
Mountain View,CA
19th Mar 2001 - present

Current Project : Synthesis & Placement for Multi-voltage & Multi-supply designs

Software Description: Development of new technology for Physical compiler & Design compiler which allows a semiconductor vendors to design chips which can have different modules operating at different voltages, thus better optimizing power & speed. This involves being able to synthesis a designers specifications taking into consideration how the different power's flow and switching-on & off various sections of the chip. This is one of the latest and hottest semi-conductor technology which needs a lot of work before it can be completely automated providing a much lesser turn-around time for such chips in future.

Some highlights of the project are:-

Placement constraints for different voltage domains
Characterization of technology libraries for a voltage range
Defining and analyzing power mesh for different voltages.
Power aware optimization tricks.

Analysis: Feasibilty of various solutions, prototyping the solutions and analyzing them for their performances.

Role

Develop functional and implementation specification of various problems.
Prototyping & implementation of various solutions
Providing early access to participating customers.
Actively consult & guide various teams about various features.

Project : Spare cells placement

Software Description: Automatic detection & placement of spare cells in the floorplan. It enables a better quality of results of the overall placement of the Chip and allows On-Silicon engineering changes.

Role: Researched the Algorithm and developed the functionality to be delivered to the customers.

 CAD Engineer
 Qualcomm Inc.
 San Diego,CA.
 7th Dec 1998-12th Mar 2001

Project:C-Compiler for Qualcomm's VLIW DSP.

Software Description: Development of a ANSI C compiler for Qualcomm's Digital Signal Processor.
Role:Design & implementation of ANSI C front-end of the compiler. It includes a parser which conforms to the ANSI C standard,all the error checking and generation of compilers intermediate representation. Currently working on it's testing and further enhancement & bug fixes.
Features: Current SLOC ~20K (comments inclusive),parser is written in YACC++ (Compiler resources Inc) which apart from providing object-oriented interface has many additional features over unix-yacc.
Front-end flow: The grammar written in YACC++ style generates an Abstract syntax tree (AST). The ANSI C semantic checks are performed on the AST. AST is then translated to higher level intermediate representation.

Involved in Development of software tools for netlist migration across different technologies.

Project: Edif to Spice netlist translator

Software Description : This tool translates an edif netlist to a spice netlist. It uses the standard cell spice netlist for a technology for it's reference.
Role: Enhancement of the existing spice parser, development of module for dumping spice from data-structures. Final design and development of tool using existing edif parser and design database.
Team Size: 1
Duration: 4 months

Project: SpiceLint

Software Description: This tool is a spice netlist checker, identifies the correctness of connectivities and expands all the includes to find any redundancies.
Role: Entire development of the tool and delivering it to the migration team.
Team Size : 1
Duration : 2 Months

Project:Spice2Spice

Software Description: This tools migrates a spice netlist from one technology to another. It scales and modifies the spice netlist according to the user specified equations.
Role: Gathering the requirement from the migration team, design and development of the entire project.
Team Size : 1
Duration : 4-5 months

 Software Design Engineer
 Texas Instruments (India) Ltd.
 Ist July1996- Oct 1998

Involved in Development & support of Software Tools for ASIC design Flow. The job consists of integrating Third party CAD tools into TI's own design flow. This is to use the best third party and our own tools to give a competitive edge to TI.

Project: Generic Front End for VHDL & VERILOG.

Scope : The GFE reads the netlist information from both verilog and VHDL. It supports co-netlist environment which means that designs blocks can be in any two languages. It provides a common Data Structure for netlist representation and an Application Procedural Interface for different tools to access the data.
Specifications generation: Specifications for VHDL front-end.
Team Size : 2 people.
Role : Development of the VHDL fron-end.
Duration : 8 months

Project : SdfAligner for TI-ASIC.

Requirements Comprehension: Gathered requirements from TI's internal customers,mainly Library team and Systems Engineers.
Software Design : Software was designed using BOOCH METHODOLOGY.
Software Design Tools : Rational Rose /C++ 4.0.
Design Analysis : The complete order analysis of the design was done and it's performance with respect to speed and memory was done.
Language Analysis : The choice of most appropiate programming language in respect to performance,complexity,implementation,maintainence and Development. The Language chosen was C++ and compiler development tools LEX & YACC.
Platforms : SOLARIS, SPARC-ULTRA & HPUX_10.2.
AdditionalTools : Clearcase for CM, Purify & Purecov for profiling and memory leaks.
Software Metrics : (a) Memory leaks < 0.05%

(b) Purify errors : 0

(c) Code coverage : 95%

Software Description : Developed a translator tool in C++/lex/Yacc for delay Alignment(SDF Parser). This tool takes the SDF from fasnet,HLDS,synopsis and parasitics and aligns them according to TI's ASIC libraries.It also merges the non-output periphiral delays of a subchip into the parent design SDF. Currently working on using multithreads to attain better speed performance.
Team Size : 1 person
Role : Complete Development of project.
Duration : 5 months.
SLOC : 16k lines.
Major Features : Handling of input file sizes > 400MB.

Memory management for page faults.

Concurrent parsing of multiple files.

Modification of byacc to support instantiable parsers.

High processing speed , 1MB input in 10 s.

Project : Tester description language translator.

Enhancement : Worked on addition of new features to the existing software.
Support : Had been involved in customer's interface and debugging.
Duration : 1 yr 6 months + till service at TI.

Project : VHDL translator for TI-ASIC.

Porting : Worked on porting the software to new VHDL parser developed by Compass Inc. The job required traversing the DLS libraries built by the parser and translating it to TI's central design database format.
Support : Had been supporting the world wide users of the software.
Duration: 1 yr 6 months + till date service at TI.

Expertise in Fields:

Expertise in writing Parsers. (see http://members.tripod.com/~ashimg/Parser.html )
Expertise in C++/LEX/YACC and OBJECT ORIENTED PROGRAMMING.
Expertise in Multithreading.

Technical Papers :

Parallelization of Parsers using Multithreading. Submitted a paper to TI's Asia Technical Conference.

Important Skills :

Advanced chip level synthesis
Physical design flows
Compiler Design

Industrial Experiences :

  Trainee
  C.M.C Ltd.
  Ist Jan 1996-24th June 1996

Developed a Module for Defence Projects Simulation and System Integration.The system was a real time system being developed for Indian Air force.

Design Analysis : I was involved in it's design feasibility and pseudo-code performance analysis.
Development : Later developed one module of systems maintenance.
Language : C
Operating System: Vertx-Sa and Solaris.
Duration : 6 months.

Education:

Birla Institute of Technology & Science,Pilani,INDIA-Master of Engineering, 1996 Software Systems.
M.M.M Engg College,Gorakhpur,INDIA-Bachelor of Engineering, 1994 Computer Engg.