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An innovative, dynamic, visionary and result oriented engineer with experience in both semiconductor CAD and EDA industry. The unique combination of the two helps in bridging the gap between a design customer's need and EDA's software expertise.

Contact Information

Mailing Address :
1276 Vicente Dr #D

Email : ,
Phone : (work) 650-584-1822 (home) 650-938-0592



Experience : 11+ yrs (Semiconductors, EDA)

Highest Education: Master of Engineering in Software Systems from Birla Institute of Technology & Science, Pilani, India (1996)

Popular Web Page :

Current : Sr R&D Engineer/Project lead at Synopsys Inc (6+ yrs)

Past : CAD engineer at qualcomm (2.5 yrs)

Software design engineer at Texas Instruments (India) Ltd
(2.5 yrs)


Professional philosophies

  • Decision making is the center of professional universe.
  • Communication is evermore crucial in today’s diverse business models.
  • Long term vision is essential even in day to day project management.


  • No technology , project or process can be deemed as successful unless it satisfies the business objectives.
  • Innovation often comes through simple ideas that are not result of systematic rational thinking.



Sr R&D Engineer/Project Lead 19th March 2001 - Present

Synopsys Inc, Mountain View, CA


Low-Power Logical & Physical Synthesis

Overview: Development of new technology for IC compiler & Design compiler which allows a semiconductor vendors to design chips which can have different modules operating at different voltages, thus better optimizing power & speed. This involves being able to synthesis a designers specifications taking into consideration how the different power's flow and switching-on & off various sections of the chip. This is one of the latest and hottest semi-conductor technology which needs a lot of work before it can be completely automated providing a much lesser turn-around time for such chips in future.


Key Role : I am the initial developer for Synopsys Multi-voltage/low-power flow. This included supporting the infrastructure, the special cells like level-shifters/isolation cells, switch cells, always-on cells etc and the entire flow right from voltage areas in the floorplan, the library modelling of special cells, synthesis and placement for special cells as well as general voltage areas.



         Voltage area creation and placement : The first project in low-power designs, implemented the definition of a voltage area in the tool and modified the placement interfaces to place cells within defined boundaries.

         Infrastructure for low-power constraints: Worked in the creation of data model to store the necessary information for low power designs.

         Library syntax and modeling for special cells : The low power designs require special cells like level-shifters, isolation cells, mtcmos switches etc. I wrote the specifications for their syntax after consulting with library vendors and were incorporated in synopsys’ liberty syntax.

         Synthesis and placement of special cells : The above mentioned cells need to be inserted in the logical netlist (circuit) and later placed based on physical constraints. I did the projects to implement the handling of special cells features, both logical & physical.

         Low Power optimizations: I had implemented two optimizations for low power flows. First , the ability to restrict the type of cells that can be used for each voltage areas and second, to have synthesis for paths that require power all the time using standard cells.

         Prototyped verilog writer for power connectivity : I did the initial prototype to enable the existing writer to also write out connectivity for power. This was later developed as solution for power specification in Synopsys flow.


Projects ideas and specifications for team

         Low Power reports : The initial flow lacked the ability to track and report the constraints for low power. Thus I created the initial project specification document with details of the requirements. I later supervised the implementation of the project by our offshore team.

         Low power design checks : I initiated and wrote the requirement and specification for checking the correctness and feasibility of various low power constraints. This project was again implemented by our offshore team.

Low Power Flow Consultations

         Contributed as a team member for Unified Power Format effort.

         Provided valuable contributions to development of power constraints for synthesis flow (power domains)

         Worked with other product groups like relative placement technology, multi-mode/multi-corner and floorplanning teams in their efforts to migrate to a low power flow.

Miscellaneous contributions

         Critical customer engagements : Have worked on numerous engagements that were essential for adoption of technologies by the users and to build customer confidence in synopsys solutions.

Understand the competitive nature of Synopsys business and define long term projects. I came up with list of enhancements/ improvements that can help the multi-voltage solution in future. This includes both runtime and analysis related enhancements and projects. Some of the analysis would not only help in reducing the MV support but should also pave way to identify and solve issues like physical feedthru, route-estimation guidance , disjoint voltage areas, automatic AO bounds generations etc

         Improve the team effectiveness and inter-team knowledge building

o       Took steps to bring the GUI features to the notice of various groups/teams so that they can use them better in debugging customer designs.

o       Creating guidelines for working with new and offshore teams, such that it leads to a win-win situation for all rather than conflict of interests



CAD Engineer 7th Dec 1998 – 12th March 2001

Qualcomm Inc, San Diego,CA


C-Compiler for Qualcomm's VLIW DSP.

Software Description: Development of a ANSI C compiler for Qualcomm's Digital Signal Processor.

Key Role: Design & implementation of ANSI C front-end of the compiler. It includes a parser which conforms to the ANSI C standard,all the error checking and generation of compilers intermediate representation. The grammar written in YACC++ style generates an Abstract syntax tree (AST). The ANSI C semantic checks are performed on the AST. AST is then translated to higher level intermediate representation . The parser was written in YACC++ (Compiler resources Inc) which apart from providing object-oriented interface has many additional features over unix-yacc.


Edif to Spice netlist translator

Software Description : This tool translates an edif netlist to a spice netlist. It uses the standard cell spice netlist for a technology for it's reference.

Key Role: Enhancement of the existing spice parser, development of module for dumping spice from data-structures. Final design and development of tool using existing edif parser and design database.



Software Description: This tool is a spice netlist checker, identifies the correctness of connectivities and expands all the includes to find any redundancies.

Key Role: Entire development of the tool and delivering it to the migration team



Software Description: This tools migrates a spice netlist from one technology to another. It scales and modifies the spice netlist according to the user specified equations.

Key Role: Gathering the requirement from the migration team, design and development of the entire project


Software Design Engineer 1st July 1996 – Oct 1998

Texas Instruments (India) ltd, Bangalore, India


Involved in Development & support of Software Tools for ASIC design Flow. The job consists of integrating Third party CAD tools into TI's own design flow. This is to use the best third party and our own tools to give a competitive edge to TI.


SdfAligner for ASIC design kit

This was a new tool in the design kit that was implemented by me, it required performing various operations on the SDF in order to perform custom back annotations of delays. It could read in the design/netlist and various SDF files from different 3rd party tools, aligns them according to TI's ASIC libraries. It also merged the non-output peripheral delays of a sub chip into the parent design SDF. Finally it would generate a single file for back annotations. I modified the yacc generator so that it can generate the object oriented parsers that could be paused and resumed by the applications. This allowed simultaneous processing/searching of multiple files while keeping linear memory and cpu usage. The software was written in C++ and followed object oriented methodology.


VHDL translator for TI-ASIC.

Worked on porting the software to new VHDL parser developed by Compass Inc. The job required traversing the DLS libraries built by the parser and translating it to TI's central design database format


Supported Various TI netlist translators

Was involved in various translators that used to translate a netlist in one language to a common data model and back to another languages. These tools provided insight to grammar of different hdls and the netlist data structures and disk caching/memory management techniques.



  • Birla Institute of Technology & Science,Pilani,INDIA-Master of Engineering, 1996 Software Systems.
  • M.M.M Engg College,Gorakhpur,INDIA-Bachelor of Engineering, 1994 Computer Engg.